• RMW operation on SRAM via AXI

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

  • AXI handshake between AW/AR-READY and B/R-RESP

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

  • How does QoS with priority and ordering allowed with AXI ID?

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

  • AXI modifiable read access

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…

  • Project on AXI Bus.

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

  • unaligned address in AXI protocol

    i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

  • Further explanation needed for VAxQOSACCEPT, AWAKEUP, ACWAKEUP and SYSO*

    Hi ARM/arktos,

    Seems like this online discussion is not working properly.

    I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

    So most likely you may not see it.

    Below is my reply to your answer to my…

  • AXI4

    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

  • AXI3 locked access

    I want to know what happens in these scenarios :
    1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1?
    2) Assume M1 is doing locked transaction, if other Master2 (M2)…

  • AXI Burst Size meaning

    Dear Community,

    I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

    a)
    I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
    When there are Bust…

  • Does CHI protocol interface use pipelines or register slice to support long distance connections ?

    Hi,

    I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

    Please confirm and where can I find relevant information for this topic.

    Thanks,

    David

  • AXI AHB APB quick reference cheat sheet

    Hi,

     I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

    So not sure of the legal ramifications of posting this elsewhere and whether…

  • AMBA AXI reset

    According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

            "All signals are sampled on the rising edge of the global clock "

         Q) Should RESET_N also  be sampled on the rising edge only?

    Section A3.1.2,  says

       "The AXI protocol…

  • Can the ARM corrupt the timing on the AXI bus

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    As the title says..

  • AXI

    What is byte lane in AXI?

  • read transfers

    In read transfres how the slave indicates the transaction is over?

  • AXI read transfer

    If the slave is not able to process read request from master, which response is expected from slave?

  • AXI

    Why burst must not cross 4kb  in AXI ?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • axi read transfers

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

  • 4k boundary in AXI

    Why the word boundary in AXI is 4k?

  • AXI transfer

    Consider Data interface is 64 bit.
    It is Write transfer.
    AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

    Scenario 1:
    Burst -> Address:0, size:3, length:1, burst_type…