• Partial Word Access to Altera Avalon Memory-Mapped Slave

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

  • Can the ARM corrupt the timing on the AXI bus

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…