• Basics: C programming for ARM - AHB transfers

    Note: This was originally posted on 18th September 2007 at http://forums.arm.com

    Hello,
    Would someone please help me about the next basic things?
    I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…

  • How to go from 32-bit to 64-bit AHB data bus

    Note: This was originally posted on 21st November 2007 at http://forums.arm.com

    Hi,
    I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…

  • Confusion over AMBA AHB hsize[] signal definition

    Note: This was originally posted on 26th February 2008 at http://forums.arm.com

    After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented…

  • AHB Multilayer

    Note: This was originally posted on 30th April 2008 at http://forums.arm.com

    In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…

  • AHB WRAP address boundaries

    Note: This was originally posted on 18th June 2008 at http://forums.arm.com

    AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…

  • AHB Arbiter

    Note: This was originally posted on 21st November 2008 at http://forums.arm.com

    Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?

  • AHB Busy states...

    Note: This was originally posted on 24th November 2008 at http://forums.arm.com

    Hello guys....

    If master is doing transfer of fixed length burst and last address is driven on bus...
    Can master drive htrans to BUSY.. at same time to put data on data bus?…

  • app crashes when compiled with OTime O3 using RVDS 4.0

    Note: This was originally posted on 1st December 2008 at http://forums.arm.com

    Hi,
    I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.

    My compiler…

  • AHB split retry response

    Note: This was originally posted on 9th December 2008 at http://forums.arm.com

    IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
    whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
    has to to issue…

  • AHB frequency

    Note: This was originally posted on 6th January 2009 at http://forums.arm.com

    Hi Friends,

       My doubt is : what is the maximum AHB clock frequency ?

    Regards,
    P.Vignesh Prabhu

  • PL031 verilog generation

    Note: This was originally posted on 19th February 2009 at http://forums.arm.com

    Pls, I need an answer to a blocking issue  :rolleyes:

    I tried to generate a verilog code for PL031 connection matrix 2x3.
    Unfortunely generated HSEL signal for each slave doesn't…

  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

    Hi,

    In AMBA AHB:-

         For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

       q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

  • AHB HREADY low not after address phase

    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

    Thanks

  • In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

    I am a Digital Verification Design Engineer.

    Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.


    I have following questions.

    1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

    2) From AHB Master side,…

  • Why the address boundary for AHB burst should not cross 1KB

    Why the address boundary for AHB burst should not cross 1KB??

    And in case of burst operation, is that every beat the address increment taken care by master?

  • Regarding retry response

    Im new to the ahb protocol can  any on give me an idea about retry response, when a retry response is generated from slave side.

  • Burst termination with BUSY transfer on AHB

    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.

    But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.

    Doesn't it mean that INCR is not terminated?

    …

  • AHB revisions from AHB3 to AHB5

    I noticed that "Multi slave select" is one of the new features in AHB5.

    But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

    I think we can do that with AHB3.

    What is the major difference between AHB3…

  • boundary concept

    Hi all,

    I am new to protocols AHB and AXI.

    can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

    Also what these boundaries are for? Does they represent the maximum slave size?

  • HREADY when no activity on bus

    Hello,

    We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

    ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

    So the questions…

  • AHB Slave HREADY

    Hello

    I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs.

    My question is Is there any specific condition for slave when it gives HREADY low?

    I am confused with HREADY signal that it is provided by the slave but at which…

  • AHB

    Hello,

    1.) Is it possible in real system that Master will send start address 0x01 ?

    If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?

    HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST…

  • why there is no split or retry responce in AXI ?

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

  • MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

    Hi,

    Facing the issue:
    "MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

    Here is the Inputs:

    We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
    connected…

  • AHB protocol

    I am newly learning AHBprotocol  i just want to know what is meaning of single cycle bus master handover?