• Interrupts and pipeline

    This is not really SoC design question, more processor type, but I didn't see such forum here. So , excuse me if not really on topic.

    My question is, is benefit of pipeline directly reduced by the number of interrupts serviced?   Because of flushing…

  • Exception handlers and interrupt

    Hi All,

            i went through this link

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html

    and related a53 vector table implementation.

    in this regard, i have a question

    1. Say a processor gets stuck in exception handler due…

  • To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured?

    I'm just trying to generate an FIQ from GIC .All the interrupts are by default grouped to Group0 and apart from setting FIQEn trying to understand what else needs to be configured..

  • Cortex-M4 setup vector table for external interrupts

    I don't want to setup the vector table for all my external interrupts. For instance I only need the timer4 IRQhandler at IRQn 30. How can I make an offset in the table? Is this necessary?

  • trustZone interrupts

    Hi

    I am playing with TrustZone as light-weight Hypervisor. My setup uses IRQ->FIQ mapping for secure interrupts but I noticed that if I disable interrupts (I bit) in the normal world also no interrupts where propagated to the secure world. So the normal…

  • WFI Instruction

    Hi,

    I want to use the wfi instruction in my code. I'm sending a command to a module and wait for the reply.

    I have configured UART communication with the module. Will it be good to use wfi() instruction? I know that it will turn  the cpu to power down…

  • How to configure Interrupt vector table ?

    Hi,
    I am using I.MX6Q Sabre sd board (cortex-a9 ). I am trying to build custom image with my own start script and ld script. The image is to be loaded with u-boot. Where should i place the Interrupt vector table? Now, when i reffered the "1.1.0_iMX6_Platform_SDK…

    • 10800.zip

  • How interrupts are routed in EL3/EL2/EL1 mode

    Sorry for basic question, 

    For ARM64, we have different interrupt vector table for each mode EL3/EL2/EL1 

    I am wondering, how a specific IRQ is routed to given mode. 

    in GIC, I am not able to find such relation 

    Thanks

    Udit

  • remapping the interrupt vector table to alternate locations in the memory map

    dear All,

    in nxp lpc 1768 i read "remapping the interrupt vector table to alternate locations in the memory map".

    for which reason one should to remap the interrupt vector table?

    regards,
    Ras

  • Dynamic memory allocation and UART

    Former Member
    Former Member

    Hi friends, I came across a problem with my UART communication.My codes are below.

    if I use

    rx_buffer = (uint8_t*)calloc(3,sizeof(uint8_t));
    HAL_UART_Receive_IT(&huart1,&rx_data,1);  and rx_buffer = (uint8_t*)realloc(rx_buffer,sizeof(uint8_t));

    program…

  • GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

    Hi,

    I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.

    How to test:

    GIC3.0:

    1. read timestamp(t01)

    2. core0 write  ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)

    3. isr in core1, read timestamp…

  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.

    I am a software engineer.

    My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?

    This question related to the implementation of the instruction…

  • Other core's view after writing ICC_SGI1R_EL1 to trigger SGI

    For example, the codes are executed in core0.

    codes:

    (1) send SGI to core1 ICC_SGI1R_EL1

    (2) set(a) = 1

    i)  Then the core1 will first see the irq or the change of variable a?

    ii)  If I add ISB between (1) and (2), what happended?

    iii)  If I add DMB (read…

  • Wake-up time from WFI

    How long does it take to wake up from from WFI once an interrupt occurs? 

    What system parameters does the answer depend on?

    What's turned off in the CPU (and elsewhere) while WFI is underway?

    I'm using NXP i.MXRT1050 (Cortex M7) and I'm experiencing…

  • Any Method to trigger/start FreeRTOS task from normal STM32 ISR??

    Hello Folks,

    What is the most effecient method to start a freeRTOS task only after an ISR is completed and flag or something set by ISR that triggers freeRTOS task.

    Lets take an example scenario , I have STM32F3 nucleo board in which i would like to toggle…