• Modbus Interface

    Hello fellas,

    I am currently working on a MOODBUS protocol with UART interface to collect data from the slave device which is a sensor and send the data to Gateway master node.

    UART interface: RS485 brakout board: Sparkfun, 8051 Micro-controller(ANU23600…

  • Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • I am trying to integrate STM32F407VG with STM32F4DIS-CAM and facing problem.

    I am new to embedded programming and need support to carry out my project. I want to capture real time video or picture using stm32F4Dis-CAM but I don't know how to start. I want to implement this project https://developer.arm.com/solutions/machine…

  • How to interface Accelerometer, EEPROM, GPS and GSM with Cortex-M?

    just help me out interfacing of GPS and GSM with Cortex-M?

  • Trouble with read write on SD card

    Hello community members.

    I have recently started working with SD card using Microchip ARM based uC SAM4. So far I have managed to initialize the HSMCI interface of SAM4 and SD card is also initialized and has responded with the card capacity and the RCA…

  • Cache Maintenance Transactions

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI read response in error case

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

  • Why AXI4 changed the definition of AxCACHE?

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

  • HREADY when no activity on bus

    Hello,

    We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

    ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

    So the questions…

  • How to handle Cache flush in ACE?

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

  • Store operations where the cache line is already cached (ACE protocol)

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

  • Removal of WID's in AMBA AXI4

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

  • AXI4 - read data interleaving

    Hi Folks,

    We need a clarification on Read Data Interleaving on AXI4

    Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

    Multiple Read commands can be executed simultaneously and data interleaving is supported…

  • What's the clock frequency for CHI interface protocol ?

    Hi,

    I was reading the CHI architecture specification but there is no mention of electrical characteristics such as

    the clock frequency for the CHI interface.

    What is the max and min frequency for CHI interface ?

    Thanks,

    David

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    As the title says..

  • AXI

    What is byte lane in AXI?

  • read transfers

    In read transfres how the slave indicates the transaction is over?

  • AXI read transfer

    If the slave is not able to process read request from master, which response is expected from slave?

  • AXI

    Why burst must not cross 4kb  in AXI ?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • axi read transfers

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

  • 4k boundary in AXI

    Why the word boundary in AXI is 4k?