• GIC-400 non-secure access

    Hi, experts

    I'm the new one porting armv8 linux. I have some problem about gic400 access.

    In the porting linux progress,CPU will switch to EL1NS.

    In gic_dist_init() function, I read the the  GICD_ISENABLERn\GICD_ICENABLERn\GICD_ITARGETSRn\GICD_IPRIORITYRn…

  • GIC-v3&4: Regarding the Acknowledge Register

    Hi all,

    I need some clarification related to acknowledge register in GICv3&4 document.

    ----------------------------------------------------------------------------------------------------------------

    8.13.11 GICC_IAR, CPU Interface Interrupt Acknowledge…

  • GIC v3&4: Programming sequence of GIC Registers

    Hi.,

    Is there any sequence in programming GIC Registers.

    1. Physical Interrupts point of view, I have followed sequence as follows:
      • GICD
      • GICR
      • GICC/ICC
    2. Coming to Virtual Interrupts point of view, I had small doubt about which module to be programmed first eith…

  • GICv3&4: Direct Injection of Virtual Interrupts

    Can anyone make me clear about direct injection of virtual interrupts.

    It is said in GICv4 that it supports direct injection of virtual interrupts,

    1. What is the advantage of  direct injection of virtual interrupts.

    2. will there be any performance…

  • why the inter-core SGI interrupt cannot be trigged on GICv3 hardware

    My hareware environment:

    1.  a ARMv8 processor , which  runs in 64bit EL3 and 32bit EL2&EL1.

    2. a GICv3 interrupt controller

    Running in 32bit hyp mode,  I try to send a SGI interrupt from core0 to core1, but core1 cannot receive this interrupt…

  • Interrupt driven TrustZone application

    Hello,

    I would like to know if a Trustzone application can be interrupt driven instead of being triggered by the non-secured world (scm).

    Thanks,

    Fabrice.

  • What will happen if one core sends SGI interrupt to another core quickly and continuously？

    I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1

    It seems that ARM does not provide guidance in processor or GIC's TRM to describe what will happen…

  • GICv3&4 : What is the purpose of Direct Injection of Virtual Interrupts.?

    Hi Everyone,

    Its true that Hypervisor inserts interrupt in the virtual machine.

    But, GICv4 also tells that it supports direct injection of virtual interrupts  which means that, interrupt can be inserted directly to VM from Redistributor without involvement…

  • Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects

    Using the GICv2, software can change the CPU interfaces targeted by an interrupt (more precisely, an SPI) by writing to the corresponding GICD_ITARGETSR. The GICv2 specification states, in the paragraph "The effect of changes to an GICD_ITARGETSR" (page…

  • The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?

    In the the arm gic arch specification  (version 2) section 3.9.2,   it has been given that for any implementation of GICv2 (with or without Security Extn)

    we can configure the GIC to generate FIQ for group 0 interrupts by enabling FIQEn…

  • GICv3 specification

    Is there any GIC architecture version 3.0 specification available ? I could not find it online.

    Thanks

  • Interrupt Routing flow in GICv3

    Hi all,

    GIC is quite an interesting topic and interrupt controller can also be said as an most important module in an SoC that routes interrupts to the Processor.

    We know that there different interrupt types in GICv3 among which SPI (Shared Peripheral Interrupt…

  • GICv2 How to resolve Multiple Interrupt appearing on a CPU

    Hi All,

    I am facing issue where, in the event of multiple interrupts on GIC in close vicinity,  I am unable to decide on which interrupt has been asserted, to service them properly.

    Details:-

    This is a simulation Setup.

    This is a multicore(4) system with…

  • GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs

    The GICv2's documentation describes as a programming error (see 5.2.4) having two or more copies of the same interrupt in the List registers.

    The notion of "same interrupt" is a bit vague when it comes to SGIs. Is it an error to program several LRs…

  • GICv2 deactivation feature.

    Hello all,

    There is one thing which is unclear for me in GICv2.

    GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a different PE. "

    In GICv2 I don't find anything…

  • GICv3 -- accessing the redistributors of other cores

    In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores.

    By contrast, GICv3 moves this configuration to redistributors…

  • GIC virtualization -- GICH_ELRSR and hardware interrupts

    Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR).

    According to the GICv{2,3,4} specification, after the virtual machine has taken the interrupt, the value of the State field in the…