Hello,

I'm using the FriendlyARM Tiny210 kit (Samsung S5PV210 ARM Cortex-A8 processor).We have loaded the OS Linux to our kit.

I have tested simple programs like led and buttons...Now, I have to test the UART program between the tiny210 and my PC, but…

I would like to use iMX6 in asymmetric mode (Windows EC7 + Linux). Is that anyhow possible? Marco

One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end

image analysis task). Due to cost or other over head reasons, he/she does not prefer to use an RTOS…

Hi,

I'm currently working on a project based on the Arria V SoC FPGA (ARM Cortex-A9 MPCore). The goal of this project is to run a high speed ethernet link.

For some reasons the customer don't want to use a Linux kernel on the ARM. His wish is to have…

We've been using TI's Panda board but it seems to give us quite a bit of trouble.  As a result we can't profile the information that we would like.  Does anyone know of any other development boards out there that has a Cortex-A9 on it?  And what experiences…

Hello Community,

in our current ASIC project we have to replace an ARM926EJ-S with a Cortex-A5.

In the moment we are facing the following problem in our bootloader:

We intend to use the high exception vectors after reset (input vinithi is tied fix to '1…

Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).

They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.

The lists…

Does anyone know if there is a list of ARM instruction set pseudo instructions?

Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and

another list of "simplified mnemonics" (=pseudo instructions…

Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…

I came across a weird behaviour when trying out my program on Raspberry Pi 2b (Cortex-A7):

When I try my PABT-handler using BKPT, the handler is entered fine, but on return the program restarts.

The restarted program returns fine from the BKPT and continues…

These days I'm using Xilinx SoC to design a software, which shares memory between Cortex-A cores and FPGA.

I've tried reserve memory in Linux and mmap() /dev/mem. The problem is if I use O_SYNC, it very slow since

my software access every byte computed…

In my little program (rpi_stub) it's time to turn on MMU and caches.

Most of it I seem to have hold of, except cache invalidations.

In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?

I understand…

I was trying to write a register context saving/restoring when I came across a weird behaviour.

My code (sorry, tried to format tens of times, but the editor WANTS to make asm a table):

I've been trying to get a watchpoint to trigger, but no luck.

There should be 4 watchpoints accordíng to DBGDIDR, DBGDSCR=0x0204000e, so there shouldn't be any problems there?

I use (just in case) the cp14 interface - write DBGWVR0 and DBGWCR0…

In a Cortex-A7 is there a register that shows which breakpoint or watchpoint has triggered a debug event?

Or what's the usual way to find out?

I understand that DFSR FS tells if the DABT took place due to debug event (IFSR for PABT) and MOE in DBGDSCR…

I'm searching for microcontrollers for a real-time motor control application. I see a lot of Cortex-M solutions for handling this, but why don't we see a lot of Cortex-A solutions specifically targeted for this?

Is there something inherent to the…

It seems Arm9 requries, but A7 doesn't.

Hi,

Following are the query regarding the ARM Cortex A7 MP Core.

In ARM Cortex A7 MP Core,facing a issue in memory mapping the registers and accessing the registers by read and write operations.

By means of the reference manual the base configuration address…

Hi All!

I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

Hi,
I am using I.MX6Q Sabre sd board (cortex-a9 ). I am trying to build custom image with my own start script and ld script. The image is to be loaded with u-boot. Where should i place the Interrupt vector table? Now, when i reffered the "1.1.0_iMX6_Platform_SDK…