• AMBA AXI reset

    According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

            "All signals are sampled on the rising edge of the global clock "

         Q) Should RESET_N also  be sampled on the rising edge only?

    Section A3.1.2,  says

       "The AXI protocol…

  • Can the ARM corrupt the timing on the AXI bus

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    As the title says..

  • AXI

    What is byte lane in AXI?

  • read transfers

    In read transfres how the slave indicates the transaction is over?

  • AXI read transfer

    If the slave is not able to process read request from master, which response is expected from slave?

  • AXI

    Why burst must not cross 4kb  in AXI ?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • axi read transfers

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

  • 4k boundary in AXI

    Why the word boundary in AXI is 4k?

  • AXI WRITE DATA CHANNEL

    Hi All,

                           I am doing single write operation to AXI slave from avalon BFM. The data and address signals

    are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

    It…

  • why we need write strobe in axi

    why we need write strobe signal in axi where we generate in our verif env

    Thanks

  • Is during AXI unaligned transfer not all WDATA bits used?

    Dear Forum,

    Can you please confirm one thing.

    When we have un-aligned transfer, do some of WDATA bits not used during that transfer?

    For example, in the below unaligned transfer WDATA[7:0] are not used for the 1st transfer. Is my understanding right?

    …

  • When Wrapping happens in AXI?

    Hi Forum,

    I cannot understand when address is being wrapped in WRAP burst.In my example, the WRAP condition never happens in other words, during BURST operation address always remains small than wrap address.

    From the spec, the wrapping happens when

    …

  • AXI WVALID before AWVALID

    what happen if WVALID asserted before AWVALID ??

  • Sampling on positive edge of clock of slave in AXI3

    How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation

  • Is there relation between the de-assertion of BVALID and BREADY signals ?

    Hi,

    I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…

  • Looking for pin/bit accurate AXI4 SystemC models

    Hi,

    I am creating a systemC model for a peripheral which has an AXI4 interface.

    Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

    Is it available from ARM, a ThirdParty vendor, or the opensource community?

  • AXI4 Burst Transactions

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI Burst Size meaning

    Dear Community,

    I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

    a)
    I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
    When there are Bust…

  • AXI ARID AWID

    What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?

  • AXI transaction failure

    Hello everyone,

    I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in the below. Write transaction is work however, read transaction…

  • unaligned address in AXI protocol

    i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…