• AXI4 Bus Bandwidth/Data Transfer increase

    Hello,

    I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

  • AXI fixed burst to a slave with narrow data width

    Hi,

    I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

    Would the the data be read from 0x100 only, with data[63:32] always…

  • AMBA AXI Write response

    I am just going through the specs of AMBA AXI.
    I've few questions.It will be great if anybody clarify
    1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
    2) How to terminate…

  • applications of amba axi

    Note: This was originally posted on 7th February 2007 at http://forums.arm.com

    hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…

  • AXI write strobes

    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    the AXI spec says:

    10.1 About unaligned transfers
    [...]
    For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…

  • AXI Read/Write ordering

    Note: This was originally posted on 24th October 2007 at http://forums.arm.com

    Hello,
       Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says that if a RAW dependency exists, the master must wait…

  • More AXI write/read ordering

    Note: This was originally posted on 25th October 2007 at http://forums.arm.com

    In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address.  Sounds like the master's assumption upon…

  • AXI Cacheable vs. Bufferable

    Note: This was originally posted on 19th November 2007 at http://forums.arm.com

    If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…

  • AXI protocol

    Note: This was originally posted on 30th December 2007 at http://forums.arm.com

    Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms

  • AXI locked access

    Note: This was originally posted on 29th May 2008 at http://forums.arm.com

    Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…

  • the usage of WSTRB signal

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Hi All,
    I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…

  • Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • Aligned and unaligned word transfers on a 64-bit bus

    address = 0x07 

    transfer size = 32 bit

    burst type  = INC

    Burst length = 4 transfers

    Can you please explain this example of unaligned word transfer on 64-bit bus.

    Why the second transfer started at 8 and not from C?

  • Lock Signal for AXI Slave

    According to what I read in AXi spec sheet, AxLOCK signals are used by the Masters for a locked access to a slave and it's the arbiter/interconnect which takes care of the AxLOCK signal.
    Am I right when I say that, "Slave doesn't care if it's Locked…

  • ACE-Lite

    Hi,

        Can anyone throw some light on ACE-Lite Slaves

         a ) Do they have inbuilt coherent caches? Can they be snooped?

         b) What type of ACE-Lite transactions are directed to them and what are the responses?…

  • STM(System Trace Macrocell)

    Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

    what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

  • Basic Understanding for AXI WRITE INCR

    Hello , 

    I am new to AXI protocol. Though I have read the document of AXI , but have some doubts on it. I have made run a write sequence (only from AXI to get the better understanding ) Please have a look at the following waveform.

    In this diagram …

  • what action will be performed by the master based on the read and write responce in axi 4?

    i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed either by normal access and by the exclusive access…

  • AXI3 write data interleaving with same AWID

    This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…

  • [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?

    Hello,

    A couple of further details on the question.

    Let's assume that I have a 64-bit data bus and a 32-bit address bus.

    A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0] = 3'b110. That is, the start address is 8 and the beat…

  • boundary concept

    Hi all,

    I am new to protocols AHB and AXI.

    can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

    Also what these boundaries are for? Does they represent the maximum slave size?

  • Three question on AXI transfers, related to disjoint byte access in a single 4 byte word, single transfer.

    I have three question on AXI transfers, and these all relate to
    a) my understanding of the spec, as all question do, and
    b) a single write transfer to a single 32-bit aligned address.

    I would like to make a single transfer to write only byte 2 at address…

  • Transfer size in AMBA AXI

    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

  • AXI-4 questions

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

  • RE: In read or write transaction in AXI.what happen if data transaction  is before address.

    Hii,

    In AXI 3 if  data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...?

    please resolve this issue...

    Thanks