• Cache Maintenance Transactions

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI read response in error case

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

  • Why AXI4 changed the definition of AxCACHE?

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

  • HREADY when no activity on bus

    Hello,

    We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

    ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

    So the questions…

  • How to handle Cache flush in ACE?

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

  • Store operations where the cache line is already cached (ACE protocol)

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

  • Removal of WID's in AMBA AXI4

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

  • SRAM for Cortex M0 -- Does It Need to Support Byte write?

    For the SRAM with Cortex M0, does it need to support byte write?

    What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

  • How can I get IP-XACT descriptions of CMSDK components?

    We use IP-XACT based automation tools, mainly for register views, so need IP-XACT description of the APB registers for the CMSDK components.

  • AHB Slave HREADY

    Hello

    I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs.

    My question is Is there any specific condition for slave when it gives HREADY low?

    I am confused with HREADY signal that it is provided by the slave but at which…

  • AHB

    Hello,

    1.) Is it possible in real system that Master will send start address 0x01 ?

    If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?

    HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST…

  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

  • Configuration options for cxapbic for 32 masters and 2 slaves

    !

    Hi everyone,

    I am new to Amba Designer tool and ARM IP.

    Barely scratching surface.

    Recently I have been trying to create a config.xml file for cxapbic (Apb bus related interconnect) for 32 masters and 2 slaves.

    I realized that the 1st 4KB are reserved…

  • why there is no split or retry responce in AXI ?

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

  • AXI narrow read with unaligned address

    Hi,

    I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

    - 32 bit data bus

    - address x0001

    - length 0 (1 beat)

    - size 1 (2 byte)

    My interpretation of the spec is that in…

  • RMW operation on SRAM via AXI

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

  • Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

    PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

    APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

  • AXI handshake between AW/AR-READY and B/R-RESP

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

  • How does QoS with priority and ordering allowed with AXI ID?

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

  • MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

    Hi,

    Facing the issue:
    "MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

    Here is the Inputs:

    We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
    connected…

  • AXI modifiable read access

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…

  • Project on AXI Bus.

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work?