Hi All,
I have doubt in ahb_lite hresp signaling when the address phase is extending.
In the following diagram transfer address c is extending because of data phase of B.
In 3rd clk cycle address C is sampled so that shall we expect the…
Hi,
In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…
Hi All ,
The following figure shows the INCR4 burst transaction.
Here the address increment is happening in each clk cycle As per AHB protocol Single outstanding address is allowed.
What are the possible adjustment has to be made for this transaction…
Difference between axi_4 and axi4_alite?
Can anyone please tell the difference btw AXI3 and AXI4.
Regards
Muthuvenkatesh
what are the possible values of strobe for a half word transfer in AXI4 lite?
Are these following values on WSTRB valid ?
-1001
-0101
-1010
hi,
what are the purpose of interconnect..?and why we nedd address routing table..in axi4
Can you please send me the AMBA APB 3.0 specification for reference.
I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?
1.I can think of invalid address as the only case. Is there any other scenario?
2. I am performing a INCR4 transfer on AHB side…
Hi
i have one doubt..in apb protocols...what is the difference between wait_state and no_wait_state in apb protocopls?
Hello All,
I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.
When I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?
Scenario : Single…
How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…
I am creating a systemC model for a peripheral which has an AXI4 interface.
Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?
Is it available from ARM, a ThirdParty vendor, or the opensource community?
Hello I want to know the calculation for
HSIZE=2 and Wrap 8
and starting address is 0x4
and how we are doing alignment ???
I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.
Eg. Burst length- Two , Burst size 16 bytes.
Please give me answers for different types of data bus width say for bus width …
What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?
Hello,
what are the additional features added or removed in AHB lite;
regards
Pavan
Hii,
Greetings !!
I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.
Please someone help me out.
Thanks in advance
Ujjwal
1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?
2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if…
Is there a limit on the number of APB slaves on the AHB to APB bridge?
I have several questions about barrier operarions.
1. how to operate barrier instructions ISB, DMB, DSB in ACE?
a) when ISB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
…
Hi Folks,
We need a clarification on Read Data Interleaving on AXI4
Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:
Multiple Read commands can be executed simultaneously and data interleaving is supported…
how to calculate the value of strobe signal in axi?
IN axi,what is unaligned data transfer??