• AHB master continues transfer after error response

    Hi Everyone,

    Consider an AHB transaction in which the AHB slave signals an error response, and the AHB master decides to continue the transfer with the present slave. Following are three waveforms that depict the AHB transfer. In all the three cases the…

  • Data during AHB Busy state

    Hi everyone,

    I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave:

    TIME: T1 T2 T3 T4
    HTRANS:    NSEQ    BUSY    SEQ     IDLE
    HADDR: 0x01 0x02 0x03 0x04
    HWDATA…

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

    I am a Digital Verification Design Engineer.

    Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.


    I have following questions.

    1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

    2) From AHB Master side,…

  • AHB slave

    1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?

    2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if…

  • Is there a limit on the number of APB slaves on the AHB to APB bridge?

    Is there a limit on the number of APB slaves on the AHB to APB bridge?