• Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data

    Hi there,

    good morning.

    I am using TMC as Embedded Trace Fifo and testing it for FULL condition.

    Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?

    So that eventually it gets full setting the FULL bit in STS…