The transfers in AHB protocols occur in two phases - address phase and data phase. Does this mean that the processor (Master) must have pipelined architecture?

Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design…

I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate…