Hello,
I'm workign in a SoC integration of a Cortex-M0 core. I've done my research but I can't seem to find an answer to an, in theory, easy question. Appreciate if someone can point me on the right direction.
We have prototyped the Cortex…
How to identify all the coresight ROM tables present in an SoC? Can APB-AP ROM table and AHB ROM tables co-exist as part of a single ROM table in the system memory?