• AHB frequency

    Note: This was originally posted on 6th January 2009 at http://forums.arm.com

    Hi Friends,

       My doubt is : what is the maximum AHB clock frequency ?

    Regards,
    P.Vignesh Prabhu

  • Bus Matrix

    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?

  • PL031 verilog generation

    Note: This was originally posted on 19th February 2009 at http://forums.arm.com

    Pls, I need an answer to a blocking issue  :rolleyes:

    I tried to generate a verilog code for PL031 connection matrix 2x3.
    Unfortunely generated HSEL signal for each slave doesn't…

  • the usage of WSTRB signal

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Hi All,
    I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…

  • ARM Cortex ICode, DCode, System buses

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …

  • Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

    Hi,

    In AMBA AHB:-

         For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

       q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

  • AHB HREADY low not after address phase

    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

    Thanks

  • In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

    I am a Digital Verification Design Engineer.

    Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.


    I have following questions.

    1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

    2) From AHB Master side,…

  • STM(System Trace Macrocell)

    Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

    what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

  • How is the PREADY signal triggered low by the Slave in an APB?

    Hi, 

    I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from  the ACCESS state? 

    If anyone could help me with this basic question, it'll be of great help thank you. :)…

  • AMBA

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

  • Assertion for Multiple Transfer on APB Bus

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

  • Project on AXI Bus.

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

  • does ARM v8 bus architecture & related IPs be compatible with v7 core?

    I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?