• Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • What's the clock frequency for CHI interface protocol ?

    Hi,

    I was reading the CHI architecture specification but there is no mention of electrical characteristics such as

    the clock frequency for the CHI interface.

    What is the max and min frequency for CHI interface ?

    Thanks,

    David

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    As the title says..

  • AXI

    What is byte lane in AXI?

  • read transfers

    In read transfres how the slave indicates the transaction is over?

  • AXI read transfer

    If the slave is not able to process read request from master, which response is expected from slave?

  • AXI

    Why burst must not cross 4kb  in AXI ?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • axi read transfers

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

  • 4k boundary in AXI

    Why the word boundary in AXI is 4k?

  • AXI transfer

    Consider Data interface is 64 bit.
    It is Write transfer.
    AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

    Scenario 1:
    Burst -> Address:0, size:3, length:1, burst_type…

  • AHB wait state insertion

      1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

      2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

  • Why do AMBA AXI does not support AxBURST of decrementing address type?

    Use case which come to my mind is.

    1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

    2. Where ever there is LIFO (Last In Fist Out) implementations.

  • AXI WRITE DATA CHANNEL

    Hi All,

                           I am doing single write operation to AXI slave from avalon BFM. The data and address signals

    are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

    It…

  • AXI read reordering depth and read interleaving depth. Are they same?AXI

    Is interleave and reorder the same concept?

    My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

  • why we need write strobe in axi

    why we need write strobe signal in axi where we generate in our verif env

    Thanks

  • AMBA AHB

    Hi,

    Can any one explain me how address decoding is done in amba ahb?

  • HRESP

    HRESP  is given  for address or data??

  • amba ahb

    hi,

    Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

    thanks in advance

  • Regarding WRAP burst calculation in AXI4

    Could you please help me on this topics in AXI4 protocal ::

    1. what is meant by Aligned and Unaligned address?

    2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

  • AXI WVALID before AWVALID

    what happen if WVALID asserted before AWVALID ??

  • In case of AXI4 lite protocol,what is the relation between BValid signal and Wvalid signal?

    In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?

  • AXI4-lite :Wready dependency on Awvalid and Wvalid

    In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.

    Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.

    What is the relation between these signals?

    and performance…

  • AHB Lite Response

    Hi All,

                               I have doubt in ahb_lite hresp signaling when the address phase is extending.

    In the following diagram transfer address c is extending because of data phase of B.

    In 3rd clk cycle address C is sampled so that shall we expect the…