• Axi4 Write Transaction

    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

  • How does QoS with priority and ordering allowed with AXI ID?

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

  • AXI modifiable read access

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…

  • unaligned address in AXI protocol

    i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

  • AXI4

    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

  • Regarding WRAP burst calculation in AXI4

    Could you please help me on this topics in AXI4 protocal ::

    1. what is meant by Aligned and Unaligned address?

    2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

  • needs some clarification

    Difference between axi_4 and axi4_alite?

  • Difference btw AXI3 and AXI4

    Hi All ,

                Can anyone please tell the difference btw AXI3 and AXI4.

    Regards

    Muthuvenkatesh

  • needs some clarifiaction

    hi,

    what are the purpose of interconnect..?and why we nedd address routing table..in axi4

  • AXI4 Burst Transactions

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …