• outsanading behaviour in AXI Vs memory latency

    I am trying to implement the axi outstanding feature in CPP, i tried to search if there is already a model in CPP, did not find alot. Is there such model ? If not, Is there any diff in terms of READ and WRITE when it comes to outstanding ?

    In additional…

  • why PSTRB signal in APB4 have four bits?

    PSTRB signal indicates which byte lanes to update during a write transfer.

    it shows that the bus contain valid data, when PSTRB[3:0]=1111.

    why we need bus instead of single bit PSTRB signal?