Hi,
I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state?
If anyone could help me with this basic question, it'll be of great help thank you. :)…
I need a clarification on PENABLE with respect to PREADY. 1) Can pready remain high for more than one cycle? 2) Does PENABLE from the master has to look for PREADY going low to deassert or it should go low the cycle next to the assertion of PREADY…