• AMBA AHB

    1)what are the different generations in AMBA AHB?

  • Basics: C programming for ARM - AHB transfers

    Note: This was originally posted on 18th September 2007 at http://forums.arm.com

    Hello,
    Would someone please help me about the next basic things?
    I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…

  • How to go from 32-bit to 64-bit AHB data bus

    Note: This was originally posted on 21st November 2007 at http://forums.arm.com

    Hi,
    I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…

  • Confusion over AMBA AHB hsize[] signal definition

    Note: This was originally posted on 26th February 2008 at http://forums.arm.com

    After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented…

  • AHB Multilayer

    Note: This was originally posted on 30th April 2008 at http://forums.arm.com

    In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…

  • AHB WRAP address boundaries

    Note: This was originally posted on 18th June 2008 at http://forums.arm.com

    AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…

  • AHB Arbiter

    Note: This was originally posted on 21st November 2008 at http://forums.arm.com

    Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?

  • AHB Busy states...

    Note: This was originally posted on 24th November 2008 at http://forums.arm.com

    Hello guys....

    If master is doing transfer of fixed length burst and last address is driven on bus...
    Can master drive htrans to BUSY.. at same time to put data on data bus?…

  • app crashes when compiled with OTime O3 using RVDS 4.0

    Note: This was originally posted on 1st December 2008 at http://forums.arm.com

    Hi,
    I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.

    My compiler…

  • AHB split retry response

    Note: This was originally posted on 9th December 2008 at http://forums.arm.com

    IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
    whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
    has to to issue…

  • AHB frequency

    Note: This was originally posted on 6th January 2009 at http://forums.arm.com

    Hi Friends,

       My doubt is : what is the maximum AHB clock frequency ?

    Regards,
    P.Vignesh Prabhu

  • PL031 verilog generation

    Note: This was originally posted on 19th February 2009 at http://forums.arm.com

    Pls, I need an answer to a blocking issue  :rolleyes:

    I tried to generate a verilog code for PL031 connection matrix 2x3.
    Unfortunely generated HSEL signal for each slave doesn't…

  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

    Hi,

    In AMBA AHB:-

         For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

       q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

  • AHB HREADY low not after address phase

    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

    Thanks

  • Why the address boundary for AHB burst should not cross 1KB

    Why the address boundary for AHB burst should not cross 1KB??

    And in case of burst operation, is that every beat the address increment taken care by master?

  • Regarding retry response

    Im new to the ahb protocol can  any on give me an idea about retry response, when a retry response is generated from slave side.

  • Burst termination with BUSY transfer on AHB

    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.

    But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.

    Doesn't it mean that INCR is not terminated?

    …

  • AHB revisions from AHB3 to AHB5

    I noticed that "Multi slave select" is one of the new features in AHB5.

    But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

    I think we can do that with AHB3.

    What is the major difference between AHB3…

  • What is expected from response if in WRAP txn in AHB is un-aligned.

    Hi,

    In spec it's mentioned that in WRAP transaction the un-aligned address will be made aligned but only when it's crossing the boundary.

    Wanted to know what's expected when the WRAP txn is started with a un-aligned address.

    Case1: Starting…

  • What purpose do wrapping BURST transfers serve?

    I've understood how it works and what happens in it, but  what is the use of having a wrapping bursts? What are some scenarios where it provides an edge?

  • State Machine for AHB-Lite Protocol

    This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor…

  • Why does an AHB slave require HBURST signal?

    HBURST specifies the type of the transfer, but what exactly does the slave/(interface) do with the HBURST signal?

  • Can a simple processor with load-store architecture support BURST?

    Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design…

  • What purpose does BURST feature in AHB serve?

    I am not able to see any visible improvements due to the BURST transfers. The same BURST transfer could be done through multiple SINGLE transfers, in the same number of cycles. Then what is te advantage of having BURST transfers?

  • How do I add AHB interface to a processor with Load Store Architecture?

    I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate…