In APB3 spec it is mentioned that "APB peripherals are not required to support the PSLVERR pin". Does it mean that both APB Master and APB Slave PSLVERR is optional or it is optional only for APB Slave? What if APB Slave supports PSLVERR but APB Master doesn't?
This comment would refer only to the peripherals (the slaves) on the bus. As the APB protocol is targeted at simple slave designs, not all will need to indicate error conditions, so those peripherals wouldn't need to have a PSLVERR output (as opposed to forcing them to have one just permanently tied to 1'b0).
However for the APB3 master it would need to have a PSLVERR input.
If the APB3 master didn't, it wouldn't then know if any of the APB3 peripherals connected to it were signaling error conditions, so potentially a system failure.
So you cannot connect APB3 peripherals that might want to signal error conditions (PSLVERR) or wait states (PREADY) to an older APB2 master which doesn't support these signals.
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