I have some question when Master used "Undefined Length" and termination with BUSY, the following is my waveform :
My question is :
1) When T5-T6, Slave still on address phase?
2) When T6-T7, Slave can drive HREADYOUT=LOW to extend data phase?
T5-T6 is the second BUSY transfer address phase, the first BUSY address phase was T4-T5.
An address phase ends when HREADY is sampled high by the master. So T5 is the end of an address phase, and T6 is the end of an address phase.
T6-T7 is the data phase of the second BUSY transfer, and the protocol states that the slave MUST provide a zero-wait OKAY response.
So NO, the slave cannot extend this BUSY transfer data phase, so your diagram is a protocol violation.
Slaves should not need to extend a BUSY transfer data phase as a BUSY transfer does not require the slave to perform any data transfer, so that is why the slave must not signal wait states for BUSY (or IDLE) transfer data phases.
Thanks very much, i finally understand "the slave MUST provide a zero-wait OKAY response" what this mean.
if slave still in data phase(have a NOSEQ or SEQ transfer is not completed), it can extend data phase whatever master is driving BUSY.
If slave is completed transfer, the slave MUST provide a zero-wait OKAY response when master is driving BUSY.
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