Coresight - observe internal design signals

We are interested in observing signals internal to the IP within our SoC. These are general state machine vector signals, error, status signals.

While Coresight provides option to trace processor execution flow, I would like to know what options are available within Coresight for the above scenario.


PS; I have seen some articles which indicate that ELA IP can do this but I want to get confirmation from experts here ...

More questions in this forum