I am trying to use AMBA TLM library developer guid in order to build a simple system of 2 masters and a memory as slave that will use AXI protocol to comunicate.
Using only the AMBA TLM library developer guid I was able to create simple master and slave that talks AXI :
Monitor mon1("mon1"); TransARMToGeneric<128> a_to_g("ARM_to_generic", ARM::TLM::PROTOCOL_AXI4); TransGenericToARM<128> g_to_a("generic_to_ARM", ARM::TLM::PROTOCOL_AXI4); Monitor mon2("mon2"); Memory mem("mem");
Can I add an interconnect to this code ?
I see the examples that are in the AMBA-PV Extensions to TLM developer guid, the DMA example and the EXcluseve example, it is not cleare on what protocol the master and slave are communicating, Can this example be configured to work in AXI ?
Thanks for your reply, "You will need to make a bridge component." what component you are refering to ? it is the bridge in the AMBA-PV user guid ? Do you have a simple example that doese such thing ? Can the AMBA TLM libray used to create an interconnect, so we can create a system with 2 MAsters compeeting over the memory ?Can we get support from ARM ?
Arm don't supply such a bridge and don't have an example, unfortunately, but if you have a valid entitle for our product e.g. Cycle Models or Fast Models, you can contact Arm support and we are happy to help you create a bridge.
Or, our EDA partners might help out in this area so if you use a 3rd party's Virtual Prototyping system, it is worth to contact them if they have such a bridge or provide you with consulting services.