If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition happens at 'Incrementing burst of undefined length'. This is a deadlock condition; something which is not clear from AHB spec.
Hi Chanpreet Singh
Just for your information I have moved your thread to the SoC forum where it should live.
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