Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?

AXI4 spec "Ordered write observation" says it "can support the Producer/Consumer ordering model with improved performance". AXI4 spec does not mention PCIE spec, but we know PCIE spec uses Producer/Consumer ordering model.

For instance, a system like this,

CPU <-> PCIE Controller <-> PCIE AXI Bridge <-> AXI4 with DEC and DDR slaves (DEC module is connected to AXI4 slave data port0 and APB register port, DDR memory module is connected to AXI4 slave data port1)

CPU performs the follwing two operations,

  1. CPU writes data to DDR
  2. CPU writes DEC APB register to start DEC

Because PCIE memory writes (both prefetchable and non-prefetchable) are posted, i.e. without responses, PCIE AXI Bridge will perform the above two operations successively with the same ID but without waiting for BRESP. Before data reaches DDR, DEC may have seen the APB register write and start read the data, so the data may be old and invalid.

If "Ordered write observation" is supported, there will be no such a problem, because it requires the interface "if two write transactions, with the same ID, are observed by all other agents in the system in the same order that the transactions are issued", i.e. if APB register write is observed by DEC, it will guarantee data write to DDR has been observable to DEC.

This ordering issue can be solved by writing a data then reading it back as follows,

  1. CPU writes data to DDR
  2. CPU read the same data back
  3. CPU writes DEC APB register to start DEC

But it's inefficient.

So is AXI4 "Ordered write observation" used to solve this issue when PCIE and AXI4 are connected? If this is the case, is it better to solve this ordering issue in the PCIE side or AXI interconnect side?

Parents
  • Your understanding here is correct - the Ordered Write Observation property is used to ensure compliance between the AXI and PCIe ordering models, such that a PCIe device can be connected into an AXI system.  It guarantees that in your below sequence:

    • CPU writes data to DDR
    • CPU writes DEC APB register to start DEC

    That the write to the DEC APB register will always be observed after the CPU write to DDR can be observed.

    If this is the case, is it better to solve this ordering issue in the PCIE side or AXI interconnect side?

    The only way you could solve this on the PCIe side is to limit the issuing capability of the PCIe device to one outstanding write.  Therefore, it is preferable that the AXI system ensures that this property is obeyed to allow for performant PCIe integration into an AXI system.

Reply
  • Your understanding here is correct - the Ordered Write Observation property is used to ensure compliance between the AXI and PCIe ordering models, such that a PCIe device can be connected into an AXI system.  It guarantees that in your below sequence:

    • CPU writes data to DDR
    • CPU writes DEC APB register to start DEC

    That the write to the DEC APB register will always be observed after the CPU write to DDR can be observed.

    If this is the case, is it better to solve this ordering issue in the PCIE side or AXI interconnect side?

    The only way you could solve this on the PCIe side is to limit the issuing capability of the PCIe device to one outstanding write.  Therefore, it is preferable that the AXI system ensures that this property is obeyed to allow for performant PCIe integration into an AXI system.

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