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AXI4-Relationships between the channels

A statement in AXI4 specification says that " the write data can appear at an interface before the write address that relates to it. This can occur when the write address channel contains more register stages than the write data channel. It is also possible for the write data to appear in the same cycle as the address."

Please explain, why the need of register stages arises here?

Is that every AXI master component needs to have register stages? Why?