Suppose A master wants to perform a SINGLE transfer.
Consider the waveform in fig below.
As depicted in the waveform. Master 1 is requesting bus at T1, arbiter samples request and drives the grant at T2. M1 samples the grant at T3 and de-asserts its request. Since M1 is performing only a SINGLE transfer so ideally grant should be changed after 1 transfer. But Arbiter will be able to sample that its a SINGLE transfer at T4 so it will grant the M2 at T4 which has been requesting from T2. M2 will be able to sample grant at T5 and can start its transfers.
So here M1 is getting the grant for 2 cycles though it has only a SINGLE transfer to perform. How this scenario should be handled with respect to both Master and Arbiter?
Or since M1 is getting grant for 1 extra transfer though its not needed, should M1 need to perform a IDLE in the 2nd cycle at T4?.
Is this the correct way to handle?