there is no strobe for read data bus in AXI, so how the master will acknowledge that which byte lanes carry the valid read data?
The master knows which data bytes it's interested in (since it's the master that requested the write), and so there's no need for the slave to signal which bytes are valid and which bytes aren't.
By contrast, for a write, the slave has no idea which bytes are intended to be valid and so the master must signal that information.
Can you please explain read operation by example.
Say we have a 32 bit data bus, and the master issues an 32 bit read (as indicated by ARSIZE). The returned RDATA would be 32'hNNxxxxxx, where the only byte the master cares about are NN.
The master knows it only needs care about RDATA[31:24] as it was the one that issued the request. The master could issue an 8 bit request instead, but perhaps for logical simplicity or for some other reason it fetches 32 bits. As long as the memory is Normal memory (i.e. there are no side effects from reading it), then this is safe to do.
Reversing your original question, who does the master need to notify about which bytes carry valid information?
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