the scenario is like :
for AXI4 FIXED burst type i am calculating lower_byte_lane and upper byte lanes for this control information
start_addr = 0001;
Number_bytes = 4;
burst_length = 4;
so now for the first transfer lower_byte_lane = 1 and upper_byte_lane = 3.
and for next transfers lower_byte_lane = 1 and upper_byte_lane = 4. why this lane value difference for FIXED burst type.AXI specification says that WSTRB value remains same for all transfers in FIXED burst.