Hi.
I have a question about timing of WLAST.
Recently, I'm running an IP test which is based on AXI4 protocol.
When I saw the waveform, I found that WLAST is being asserted before WVALID and even before the address being issued.
I thought it is quite strange because it means that the IP is notifying that the transaction is the last of the burst even before issuing it.
But according to the AXI document it seems that there aren't any mentions about relationship between WLAST and other signals.
Isn't it a protocol violation?
If not, is it fine to leave it for correct operation?
When the xVALID signal for any channel is low, the other signals on the channel are undefined, so seeing WLAST asserted before WVALID doesn't mean anything. It is only once WVALID is asserted that the WLAST assertion indicates the end of the data transfer sequence is being signalled.
And for write transactions you could see the WLAST transfer complete before the associated AW channel transfer. The AXI protocol does not require the write address to be issued by the master or received by the slave before write data. This could happen if for example you had extra registering on the AW channel compared to the W channel, so perhaps a master issuing AW and W at the same time (quite reasonable), but by the time the transfers reach the target slave the W transfer is a few cycles ahead of the AW transfer.
In most cases I would expect the slave will need to know the AW information before it can accept any W transfers (unless that slave could just buffer all data transfers until it knows what to do with them), so in that case all the slave needs to do is deassert WREADY to stall acceptance of W channel transfers until it has received an AW transfer telling it what to do with W channel transfers.
So no protocol violations from what you describe.