AXI4 document says that when a master issues multiple transactions to same / overlapping address with same ID, the order of arrival at the slave must be the same as the order of issue.
I think it means if transactions are not for the same address, they can be out of order even if they have same ID.
Is it correct?
If so, when transactions have the same ID how can I distinguish whether transactions are reorderable or not?
The clearest description of this is given in A6.1 in the AXI Spec:
"The principles are that for transactions with the same ID:
• transactions to any single peripheral device, must arrive at the peripheral in the order in which they are issued, regardless of the addresses of the transactions
• memory transactions that use the same, or overlapping, addresses must arrive at the memory in the order in which they are issued."
Hyunkyu said:I think it means if transactions are not for the same address, they can be out of order even if they have same ID.
Is it correct?
If they are to the same peripheral device, then no they must remain in order regardless of the address. In effect, for an interconnect this would normally mean transactions to the same interface. If they are to different devices, then they can arrive out of order. However, the responses must be returned to the original master in the correct order of issue.
Hyunkyu said:If so, when transactions have the same ID how can I distinguish whether transactions are reorderable or not?
Each device that handles a transaction will either be aware that the transaction is going to different peripheral (such as an interconnect) and can determine the ordering, or if it isn't aware, then it must maintain the order between the transactions.
So, if a master issues transactions with same ID to same peripheral, they may arrive at slave in same order.
And if a master issues transactions with same ID to different peripheral which have overlapping address, they also may arrive at each slave in same order.
And last, all responses with same ID will be arrive at master in order.
Is it right?
For your first statement, master transactions with the same ID to the same peripheral MUST arrive in the same order.
For your second statement, peripherals cannot have overlapping addresses. Each must have a unique address range so that the "interconnect" knows which specific peripheral to route them to/from.
For your third statement, yes. Otherwise the master wouldn't know which transaction each response referred to.
Then, what does the state "When a master issues multiple transactions to same / overlapping address with same ID, the order of arrival at the slave must be the same as the order of issue" mean on AXI4 document?
If it is just metioning only about same ID to the same peripheral, there is no difference between AXI3 and AXI4 spec.
Is this quote from section A6.2 of the AXI4 protocol ?
if so, this is for "normal" memory types where the system behaviour isn't affected by the order of transactions reaching the slave when they do NOT overlap, but where they do overlap you need to ensure that the last issued transfer is the one that is last updated, so that the memory slave is left in the master's intended state.
For "device" memory types, ordering of ALL transfers is important, overlapping or not, as this could affect the programming steps of a device.
Overlapping describes two transfers to the same slave that have the same one or more bytes included in the transfer. These overlapping transfers MUST be to the same slave.
Now I understand what it means.
But I think multiple transactions with SAME ID will always arrive at the target in the same order of issue.
If not, slave may not be able to respond in order.
So, order of arrival may be same no matter what the memory type of the target is.
Is there any reason to distinguish the case for the Device memory and the others?
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