PL031 verilog generation

Offline nicolan nicolan over 6 years ago

Note: This was originally posted on 19th February 2009 at http://forums.arm.com

Pls, I need an answer to a blocking issue

I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't work properly.
In "AxiToAhbWrapper" output verilog file, in fact, following assign appears:

assign HSEL =1'b1;

and because this block is "copied" for all the master interface inside, then all "HSELx" signals are put high.

What's appens?!

regards
Nicola

0 Offline nicolan nicolan over 6 years ago

Note: This was originally posted on 20th February 2009 at http://forums.arm.com

Thanks JD,

HTRANS utilization, I think, is the best way to proceed.

rgds,

Nicola
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0 Offline Colin Campbell over 6 years ago

Note: This was originally posted on 20th February 2009 at http://forums.arm.com

Hi Nicola,

The PL301 (I assume this is what you meant) is usually IP licensed directly from ARM, so you would be much better sending your questions to them directly rather than using a more public forum such as this. Their support guys are probably best placed to support their own IP.

I would guess though that the answer to your questions is that this AHB port is designed to support just one AHB slave, hence the single HSEL output, and if there are no transfers coming to your slave, the HTRANS signal will probably be indicating IDLEs.

If each of your PL301 outputs are AHB ports, each would then have a single AHB HSEL signal, each driven permanently high, and the connected slaves would be permanently selected, using HTRANS to define when a transfer is occuring (all perfectly valid).

You can also specify that the AHB port appears as an AHB master, so no HSEL signal, and you then add your own external AHB decoder block, which will generate the HSEL outputs you want, and active only when you want.

But if you've got a support agreement for PL301 with ARM (or whoever you got the PL301 from), you would get a more definite answer using that channel.

JD
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PL031 verilog generation

AXI4 transaction attributes 0

AMBA 5 CHI Link Layer (L-Credit Return) 0

Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? 0

BUSY transfer just before the last transfer in a burst by a AHB Master. 0

AMBA AXI reset 0