Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
System
Jump...
Cancel
System
SoC Design forum
Bus Matrix
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
State
Not Answered
Replies
4 replies
Subscribers
71 subscribers
Views
3909 views
Users
0 members are here
AMBA
Cortex-M3
Bus Architecture
Cortex-M
Related
Bus Matrix
Offline
Felix Varghese
over 7 years ago
Note: This was originally posted on 28th January 2009 at
http://forums.arm.com
What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
Parents
0
Offline
Peter Harris
over 7 years ago
Note: This was originally posted on 28th January 2009 at
http://forums.arm.com
> so is the core the only master here and other devices are slaves?
Yes. A master is anything which can initiate a transaction on the bus - so a CPU, a DMA engine, etc. A slave is something which recieves a transaction sent by a master (memory device, peripheral, bus bridge).
> And what is the point of this kind of an arrangement?
The matrix design philosophy really originated because of complex ASIC requirements, such as cellular handset designs. In these you often have 10 - 20 masters (mutliple ARM cores, DSPs, custom logic accelerators, GPUs, etc), and a large number of slaves (multiple memory ports, both on-SoC and off-SoC, and peripheral regions).
In these designs you might have a memory slave that you want the baseband modem DSP to see, but that you do not want the GPU to be able to see. By configuring the matrix properly when you synthesize the bus, you can easily block this memory transaction simply by ensuring that the connection doesn't exist in the RTL.
The other important thing to note is that most modern bus architectures are conceptually point to point links between individual masters and slaves. Each point to point link can have different performance characteristics if needed, such as higher priority or a wider bus width.
For a microcontroller the "matrix" might be quite small - but the same principles apply.
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Reply
0
Offline
Peter Harris
over 7 years ago
Note: This was originally posted on 28th January 2009 at
http://forums.arm.com
> so is the core the only master here and other devices are slaves?
Yes. A master is anything which can initiate a transaction on the bus - so a CPU, a DMA engine, etc. A slave is something which recieves a transaction sent by a master (memory device, peripheral, bus bridge).
> And what is the point of this kind of an arrangement?
The matrix design philosophy really originated because of complex ASIC requirements, such as cellular handset designs. In these you often have 10 - 20 masters (mutliple ARM cores, DSPs, custom logic accelerators, GPUs, etc), and a large number of slaves (multiple memory ports, both on-SoC and off-SoC, and peripheral regions).
In these designs you might have a memory slave that you want the baseband modem DSP to see, but that you do not want the GPU to be able to see. By configuring the matrix properly when you synthesize the bus, you can easily block this memory transaction simply by ensuring that the connection doesn't exist in the RTL.
The other important thing to note is that most modern bus architectures are conceptually point to point links between individual masters and slaves. Each point to point link can have different performance characteristics if needed, such as higher priority or a wider bus width.
For a microcontroller the "matrix" might be quite small - but the same principles apply.
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Children
No data
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
Behaviour of CHI Receiver during race condition from RUN to DEACTIVATE
0
AMBA
AMBA 5 CHI
CHI
Bus Architecture
AMBA 5
4181
views
0
replies
Started
4 months ago
by
amit
Not Answered
In APB, Why do we use enable signal? (Don't care about PREADY)
0
4518
views
0
replies
Started
4 months ago
by
INNS
Not Answered
DC/DC Controller SoC
0
5015
views
1
reply
Latest
5 months ago
by
Andy Neil
Not Answered
AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed?
+1
System on Chip (SoC)
AMBA 5 CHI
CHI
Cache Architecture
5206
views
1
reply
Latest
5 months ago
by
IPDeveloper
Not Answered
AXI4 transaction attributes
0
5024
views
0
replies
Started
5 months ago
by
Ravi V.
<
>
View all questions in SoC Design forum