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Bus Matrix

Felix Varghese
Offline over 6 years ago
Note: This was originally posted on 28th January 2009 at http://forums.arm.com

What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
  • 0 Offline over 6 years ago
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    More modern ASIC designs have a complex N-to-M bus mapping (multiple masters, with multiple slaves, but not everything can see everything else). This assignment is a little like a matrix (rows are masters, slaves are columns, and each cell determines the visbility of that slave to that master).


    Can you ellaborate? I mean in this case we have two buses coming out of the core into the bus matrix (instruction and data), and many going out (to SRAM, peripherals, flash, etc) so is the core  the only master here and other devices are slaves? And what is the point of this kind of an arrangement?
  • 0 Offline over 6 years ago
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    > so is the core the only master here and other devices are slaves?

    Yes. A master is anything which can initiate a transaction on the bus - so a CPU, a DMA engine, etc. A slave is something which recieves a transaction sent by a master (memory device, peripheral, bus bridge).

    > And what is the point of this kind of an arrangement?

    The matrix design philosophy really originated because of complex ASIC requirements, such as cellular handset designs. In these you often have 10 - 20 masters (mutliple ARM cores, DSPs, custom logic accelerators, GPUs, etc), and a large number of slaves (multiple memory ports, both on-SoC and off-SoC, and peripheral regions).

    In these designs you might have a memory slave that you want the baseband modem DSP to see, but that you do not want the GPU to be able to see. By configuring the matrix properly when you synthesize the bus, you can easily block this memory transaction simply by ensuring that the connection doesn't exist in the RTL.

    The other important thing to note is that most modern bus architectures are conceptually point to point links between individual masters and slaves. Each point to point link can have different performance characteristics if needed, such as higher priority or a wider bus width.

    For a microcontroller the "matrix" might be quite small - but the same principles apply.
  • 0 Offline over 6 years ago
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    The bus is the "glue" that links all of the components (process, memory, etc) together and enables them to communicate.

    More modern ASIC designs have a complex N-to-M bus mapping (multiple masters, with multiple slaves, but not everything can see everything else). This assignment is a little like a matrix (rows are masters, slaves are columns, and each cell determines the visbility of that slave to that master).
  • 0 Offline over 6 years ago
    Note: This was originally posted on 31st January 2009 at http://forums.arm.com

    ...And what is the point of this kind of an arrangement?


    The bus-matrix on the Cortex-M3 is a basic arbiter and router, connecting three sources of transactions (load/stores from the core, instruction fetches from the core and debug read/writes from the debug access port) to the M3's four destinations, the instruction and data code busses, the system bus and the NVIC/private-peripheral space.

    In the best case this should allow multiple transactions to be handled simultaneously, e.g. instruction fetch from instruction-code-bus in parallel with data store to system bus; in the worst case it ensures that simultaneous requests from multiple sources to the same destination occur in the correct order based upon the priority assigned to the source.

    hth
    s.
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