Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
System
Jump...
Cancel
System
SoC Design forum
AHB Busy states...
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
State
Not Answered
Replies
2 replies
Subscribers
71 subscribers
Views
2978 views
Users
0 members are here
AMBA
Bus Architecture
AHB
Related
AHB Busy states...
Offline
LEO LEO
over 7 years ago
Note: This was originally posted on 24th November 2008 at
http://forums.arm.com
Hello guys....
If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?? (assume write transfer..)
in simple words....
BUSY htrans is possible at the end of fixed length burst??
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Suggested Answer
APB4 PSTRB
0
3925
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
AHB Lite
0
4880
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
Ulink pro debugging in custom SoC
0
Custom SoC
ulinkpro
SoC Verification
3461
views
0
replies
Started
4 months ago
by
ronit
Not Answered
Design considerations for implementing flash program download
0
CoreSight Architecture
SWD
Debug Access Port (DAP)
10388
views
3
replies
Latest
4 months ago
by
Mohamed Nasser
Not Answered
Using sram instead of a flash memory in ASIC implementation
0
SoC Implementation
SRAM
SoC FPGA
Debugging
4130
views
0
replies
Started
4 months ago
by
Mohamed Nasser
<
>
View all questions in SoC Design forum