AHB response relation with data

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SoC Design forum AHB response relation with data

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Note: This was originally posted on 30th September 2008 at http://forums.arm.com

Hi,

I have an issue regarding AHB responses relation
with data in case of AHB write transfers.

As we know that the address phase of any transfer occurs during
the data phase of the previous transfer (pipelined operation).

So if we consider all signals to be synchronous to AHB clock, does it mean
that data of any transfer occurs during response of previous transfer.

Please refer to the attached waveform and explain if its true.

Thanks,
Hari

AXI4 transaction attributes 0

AMBA 5 CHI Link Layer (L-Credit Return) 0

Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? 0

BUSY transfer just before the last transfer in a burst by a AHB Master. 0

AMBA AXI reset 0