Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
System
Jump...
Cancel
System
SoC Design forum
AHB Bufferable/Non-bufferable write
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
State
Not Answered
Replies
8 replies
Subscribers
71 subscribers
Views
6988 views
Users
0 members are here
AHB.AMBA
Bus Architecture
Related
AHB Bufferable/Non-bufferable write
Offline
Hariprem Arora
over 7 years ago
Note: This was originally posted on 12th September 2008 at
http://forums.arm.com
Hi,
Please clarify the following issue related to AHB write:
If HPROT[2] = 1, AHB write is bufferable and we need to provide OKAY response as soon as the AHB slave interface receives data without caring that the data is actually written into the memory or not.
if HPROT[2] = 0, AHB write is non-bufferable, AHB slave interface needs to provide response to the master only when the data is actually written into the memory.
The issue is that if we see this non-bufferable transaction, the state of HRESP will by default be OKAY (HREADY is HIGH to accept the next data) and it means that we are providing the response in advance for non-bufferable write.
Please clarify how to distinguish between the two transactions.
If possible, please provide waveforms for INCR undefined length & non-bufferable write
Parents
0
Offline
Hariprem Arora
over 7 years ago
Note: This was originally posted on 15th September 2008 at
http://forums.arm.com
Hi JD,
Thanks for clarification regarding response from AHB slave for non-bufferable write.
so from the explanation, I understood that AHB slave has to pull HREADY LOW to insert wait state.
Does it mean AHB slave can insert wait state for each data transacted in a burst to give actual destination slave response. Is this feasible with regards to the throughput.
Hari
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Reply
0
Offline
Hariprem Arora
over 7 years ago
Note: This was originally posted on 15th September 2008 at
http://forums.arm.com
Hi JD,
Thanks for clarification regarding response from AHB slave for non-bufferable write.
so from the explanation, I understood that AHB slave has to pull HREADY LOW to insert wait state.
Does it mean AHB slave can insert wait state for each data transacted in a burst to give actual destination slave response. Is this feasible with regards to the throughput.
Hari
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Children
No data
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Suggested Answer
APB4 PSTRB
0
3925
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
AHB Lite
0
4880
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
Ulink pro debugging in custom SoC
0
Custom SoC
ulinkpro
SoC Verification
3461
views
0
replies
Started
4 months ago
by
ronit
Not Answered
Design considerations for implementing flash program download
0
CoreSight Architecture
SWD
Debug Access Port (DAP)
10388
views
3
replies
Latest
4 months ago
by
Mohamed Nasser
Not Answered
Using sram instead of a flash memory in ASIC implementation
0
SoC Implementation
SRAM
SoC FPGA
Debugging
4130
views
0
replies
Started
4 months ago
by
Mohamed Nasser
<
>
View all questions in SoC Design forum