AHB Multilayer

System

SoC Design forum AHB Multilayer

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Offline Jesuraj vinoth Joseph over 6 years ago

Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic doubt is that apart from the interconnect matrix do we hav any slave mux and decoder.

AXI4 transaction attributes 0

AMBA 5 CHI Link Layer (L-Credit Return) 0

Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? 0

BUSY transfer just before the last transfer in a burst by a AHB Master. 0

AMBA AXI reset 0