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AXI protocol

neha004
Offline over 6 years ago
Note: This was originally posted on 30th December 2007 at http://forums.arm.com

Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms
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  • 0 Offline over 6 years ago
    Note: This was originally posted on 31st December 2007 at http://forums.arm.com

    In AXI, a transfer is not completed until the bus master receive the response from the read data channel or write response channel.  Also after a bus master issue a transfer, it can issue another transfer without waiting for the first one to complete. If the order of the responses coming back from the slaves arrived in different order from the order that the transfers were issued, we can call it out of order completion.

    Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. In this case, instead of waiting for one sequence to complete before the other sequence start, the AXI infrastructure can interleave the write data sequences together to avoid wasting idle cycles on the bus.
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  • 0 Offline over 6 years ago
    Note: This was originally posted on 31st December 2007 at http://forums.arm.com

    In AXI, a transfer is not completed until the bus master receive the response from the read data channel or write response channel.  Also after a bus master issue a transfer, it can issue another transfer without waiting for the first one to complete. If the order of the responses coming back from the slaves arrived in different order from the order that the transfers were issued, we can call it out of order completion.

    Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. In this case, instead of waiting for one sequence to complete before the other sequence start, the AXI infrastructure can interleave the write data sequences together to avoid wasting idle cycles on the bus.
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