I just finish studying AMBA 4 AXI and AMBA 3 AXI protocol. I'm confused about something.
In chapter A4.1, transaction type and attribute, mentioning about AxCACHE and its description . But I can't get the meaning of some features as below
For write, a number of different transactions can be merged together , and read transaction can be prefetched. Could someone explain it more precise for me?
I'm so appreciate for that.
I would recommend using the AXI4 definition of this bit, as it was changed to more accurate describe the functionality. In AXI4, AxCACHE is the Modifiable bit.
What this bit really means is whether this access is going to Normal memory (AxCACHE = 1) or Device memory, where Device memory generally requires that the transaction attributes are not changed as they travel through system as the accesses have side effects.
If AxCACHE = 1, we can then modify the transaction attributes meaning for example that we can merge accesses. For example, if you have separate byte access to 0x0, 0x4 and 0x5, then on a 64 bit bus we could merge these three accesses into a single transaction with AxSIZE = 64 bit, where if this was a write we would use the WSTRBs to indicate which bytes were valid.
If AxCACHE = 0 in the above example, then the system would not be allowed to optimise these 3 byte accesses into a single transaction.
With regards to prefetching, accesses to Device memory (AxCACHE = 0) do not allow prefetching as these areas can have side effects. For example, reading a FIFO entry might remove the data from the head of the FIFO, and so it's not safe to prefetch to this location.
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