I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
Hi SelvamThangam,
I don't think there is such a constraint in AXI4.
In fact I think the purpose of the BID signal is to allow "decoupling" the write and response channels.
See also all the assertions for write address and write data channels:
https://developer.arm.com/docs/dui0534/latest/protocol-assertions-descriptions/axi4-and-axi4-lite-protocol-assertion-descriptions/write-address-channel-checks
https://developer.arm.com/docs/dui0534/latest/protocol-assertions-descriptions/axi4-and-axi4-lite-protocol-assertion-descriptions/write-data-channel-checks
There is no mention of bresp in there.
Best regards,
Vincent.