Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design doesn't have support for a lot of features AHB can offer, like HREADY and HRESP support, etc.
Can it be made to take advantage of BURST transfers (AHB-Lite) ? If so, what changes in the design might be required?