Can a simple processor with load-store architecture support BURST?

Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design doesn't have support for a lot of features AHB can offer, like HREADY and HRESP support, etc.

Can it be made to take advantage of BURST transfers (AHB-Lite) ? If so, what changes in the design might be required?

  • If the processor is really simple, it probably can't make much use of HBURST other than signalling SINGLE or undefined length INCR (if it knows that an access is sequentially related to the previous access).

    You would only really be able to make use of the longer defined length HBURST types if your processor knew that its current access was part of a 4, 8 or 16-beat sequential burst of accesses (unlikely if it really is "simple").

    A master signalling all transfers as SINGLE or INCR is quite normal, but as explained in my replies to your other questions it gives the rest of the system less information about what the master next intends to do, so doesn't allow other system components to optimise their responses.

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