I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate data bus port must be present?
Also, in general, how do I proceed in order to make it AHB compatible?
You would need to generate 2 separate data buses to make it AHB compatible, as that is what other AHB components will expect.
So you will need to add logic inside your processor's AHB interface to control when you drive the shared internal data bus with read data from HRDATA. HWDATA I guess could just be whatever is on the internal shared data bus as HWDATA is undefined during read accesses (undefined not requiring it to be 0 or static).
I realise this may not be the right place to ask this, but can you as well help me with the Verilog code of multiplexing one single data bus into HRDATA and HWDATA? I'm having trouble dealing with the inout port.
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