I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate data bus port must be present?
Also, in general, how do I proceed in order to make it AHB compatible?
I realise this may not be the right place to ask this, but can you as well help me with the Verilog code of multiplexing one single data bus into HRDATA and HWDATA? I'm having trouble dealing with the inout port.