We are using the Arm® Artisan® 14nm 14LPP High-Speed Single-Port SRAM.
We ordered these SRAMs by ARM mem complier and plan to use external power gating on these SRAMs.
And also, we do not need to use the retention mode of the SRAM, just use enable mode, disable mode and power down mode of the SRAM.
So, we just plan to connect the VDDCE and VDDPE power pins to one same power net to simplify our design.
Thus the VDDCE and VDDPE will power up or power down at the same time.
Can anyone help to check/confirm whether the usage/power connections mentioned above is safe or not? Any risks here?
We have some concerns because we found below descriptions in the ARM® Artisan® 14nm 14LPP Power Management document, which means VDDCE and VDDPE can not be power up/power down together in power down mode.
For retention and power down modes:• VDDPE must be powered down before VDDCE,• VDDPE must be powered up after VDDCE, to prevent forward biasing of PN diodes where areas ofP-diffusion are connected to VDDPE and areas of N-WELL are connected to VDDCE.