Hello I want to know the calculation for
HSIZE=2 and Wrap 8
and starting address is 0x4
and how we are doing alignment ???
HSIZE=2 means 32-bit transfers, so 4 byte address increments.
The wrapping boundary for an 8-beat, 4 byte WRAP burst will be on multiples of 8x4 bytes, so 32-byte boundaries (HADDR multiples of 0x20).
So starting at 0x4 the WRAP8 burst will access 0x4, 0x8, 0xC, 0x10, 0x14, 0x18 then 0x1C. As the next (8th) address increment would hit the wrap boundary, the next (and final) access would instead wrap back to 0x0.
The HTRANS value for the 0x0 access is still SEQ because this is a sequential expected step for this WRAP burst sequence (it isn't a NONSEQ step).
Hopefully that answers your question.
Here I am agree with the explanation but the alignment scenario is still pending
Like what will be our address alignment boundary, how we will calculate ?
As Colin explained, the wrapping boundary for an 8-beat, 4 byte WRAP burst will be on multiples of 8x4 bytes, so 32-byte boundaries (HADDR multiples of 0x20). Examples:
1) starting at 0x4 -> 0x8 -> 0xC -> 0x10 -> 0x14 -> 0x18 -> 0x1C -> 0x0
2) starting at 0x10 -> 0x14 -> 0x18 -> 0x1C -> 0x0 -> 0x4 -> 0x8 -> 0xC
3) starting at 0x34 -> 0x38 -> 0x3C-> 0x20 -> 0x24 -> 0x28 -> 0x2C -> 0x30
The other 2 examples which is given here, Does it satisfies the address alignment of AHB ?
In the third examples, how the next address is come out to 0x20 from its previous address 0x3C, as the boundary is 0x20 only ?
Could you Please explain it clearly, Thanks in advance
The 3 examples in Vanhealsing's reply from 2 years ago are all correct and meet all the address alignment requirements of the protocol.
With an 8-beat 4 byte burst you have 32-bytes total to transfer (0x20 in hex), so the "wrap_boundary" the burst will wrap down to in example 3 is 0x20, as the burst will wrap if an address increment were to hit the next higher wrap boundary at 0x40.
If there is something that worries you here, can you expand on your concern ?
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