• Turning on MMU and caches on Cortex-A7?

    In my little program (rpi_stub) it's time to turn on MMU and caches.

    Most of it I seem to have hold of, except cache invalidations.

    In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?

    I understand…

  • L1 Cache Eviction Corrupting DDR on A9

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…