• Cortex-A5 sets instr_pc to 0x00000008 after enabling MMU and using high exception vectors

    Hello Community,

    in our current ASIC project we have to replace an ARM926EJ-S with a Cortex-A5.

    In the moment we are facing the following problem in our bootloader:

    We intend to use the high exception vectors after reset (input vinithi is tied fix to '1…

  • Cortex-A7 instruction lists

    Just in case someone needs them, I made ARM and Thumb mode lists of Cortex-A7 instructions (because I didn't find them in the net).

    They are generated from ARMv7-A/R ARM with a simple AWK-script and then edited, so they may contain errors.

    The lists…

  • ARM instruction set pseudo instructions

    Does anyone know if there is a list of ARM instruction set pseudo instructions?

    Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and

    another list of "simplified mnemonics" (=pseudo instructions…

  • How to access the memory mapped debug registers?

    Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR, but it seems that in Cortex-A7 it's not accessible…

  • ARMV7A virtualization

    Hi,

    I am working on a hardware platform having 2 Cortex-A15 cores (with virtualization extensions). For routing IRQ's at PL2 to PL3 ( to hypervisor mode), I am setting HCR.IMO bit and it is working fine for core-0. If I set the HCR.IMO for core-1, will…